@article{flash:WZ1994,
   Author = {Michael Wu and Willy Zwaenepoel},
   Title = {eNVy: a non-volatile, main memory storage system},
   Journal = {SIGOPS Oper. Syst. Rev.},
   Volume = {28},
   Number = {5},
   Pages = {86-97},
   Note = {195506},
   Year = {1994} }

@article{flash:BJ1991,
   Author = {Blalock, T. N. and Jaeger, R. C.},
   Title = {A high-speed clamped bit-line current-mode sense amplifier},
   Journal = {Solid-State Circuits, IEEE Journal of},
   Volume = {26},
   Number = {4},
   Pages = {542-548},
   Note = {0018-9200},
   Year = {1991} }



@inproceedings{flash:CLF+2008,
   Author = {Cernea, R. and Long, Pham and Farookh, Moogat and Siu, Chan and Binh, Le and Yan, Li and Shouchang, Tsao and Tai-Yuan, Tseng and
   Khanh, Nguyen and Li, J. and Hu, J. and Jong, Park and Hsu, C. and Fanglin, Zhang and Kamei, T. and Nasu, H. and Kliza, P. and Khin, Htoo and
   Lutze, J. and Yingda, Dong and Higashitani, M. and Junhui, Yang and Hung-Szu, Lin and Sakhamuri, V. and Li, A. and Feng, Pan and Yadala, S. and
   Taigor, S. and Pradhan, K. and Lan, J. and Chan, J. and Abe, T. and Fukuda, Y. and Mukai, H. and Kawakamr, K. and Liang, C. and Ip, T. and
   Shu-Fen, Chang and Lakshmipathi, J. and Huynh, S. and Pantelakis, D. and Mofidi, M. and Quader, K.},
   Title = {A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm},
   BookTitle = {Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International},
   Pages = {420-624},
   Year = {2008} }



@misc{flash:CJS+2003,
   Author = {Chanik, Park and Jaeyu, Seo and Sunghwan, Bae and Hyojun, Kim and Shinhan, Kim and Bumsoo, Kim},
   Title = {A low-cost memory architecture with NAND XIP for mobile embedded systems},
   Publisher = {ACM},
   Note = {944684
138-143},
         Year = {2003} }



@inproceedings{flash:CYW+1999,
   Author = {Chung, S. S. and Yih, C. M. and Wu, S. S. and Chen, H. H. and Gary, Hong},
   Title = {A Spice-compatible flash EEPROM model feasible for transient and program/erase cycling endurance simulation},
   BookTitle = {Electron Devices Meeting, 1999. IEDM Technical Digest. International},
   Pages = {179-182},
   Year = {1999} }



@inproceedings{flash:ES2005,
   Author = {Ekman, M. and Stenstrom, P.},
   Title = {A Cost-Effective Main Memory Organization for Future Servers},
   BookTitle = {Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International},
   Pages = {45a-45a},
   Year = {2005} }



@inproceedings{flash:HFK+2005,
   Author = {Hara, T. and Fukuda, K. and Kanazawa, K. and Shibata, N. and Hosono, K. and Maejima, H. and Nakagawa, M. and Abe, T. and Kojima, M.
   and Fujiu, M. and Takeuchi, Y. and Amemiya, K. and Morooka, M. and Kamei, T. and Nasu, H. and Kawano, K. and Chi-Ming, Wan and Sakurai, K. and
   Tokiwa, N. and Waki, H. and Maruyama, T. and Yoshikawa, S. and Higashitani, M. and Pham, T. D. and Watanabe, T.},
   Title = {A 146 mm/sup 2/ 8 Gb NAND flash memory with 70 nm CMOS technology},
   BookTitle = {Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International},
   Pages = {44-584 Vol. 1},
   Year = {2005} }



@inproceedings{flash:IMS+1989,
   Author = {Itoh, Y. and Momodomi, M. and Shirota, R. and Iwata, Y. and Nakayama, R. and Kirisawa, R. and Tanaka, T. and Toita, K. and Inoue, S.
   and Masuoka, F.},
   Title = {An experimental 4 Mb CMOS EEPROM with a NAND structured cell},
   BookTitle = {Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International},
   Pages = {134-135, 314},
   Year = {1989} }



@article{flash:IIS+1995,
   Author = {Iwata, Y. and Imamiya, K. and Sugiura, Y. and Nakamura, H. and Oodaira, H. and Momodomi, M. and Itoh, Y. and Watanabe, T. and Araki,
   H. and Narita, K. and Masuda, K. and Miyamoto, J. I.},
   Title = {A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM},
   Journal = {Solid-State Circuits, IEEE Journal of},
   Volume = {30},
   Number = {11},
   Pages = {1157-1164},
   Note = {0018-9200},
   Year = {1995} }



@article{flash:KSL+1997,
   Author = {Jin-Ki Kim and Sakui, K. and Sung-Soo Lee and Itoh, Y. and Suk-Chon Kwon and Kanazawa, K. and Ki-Jun Lee and Nakamura, H. and
   Kang-Young Kim and Himeno, T. and Jang-Rae Kim and Kanda, K. and Tae-Sung Jung and Oshima, Y. and Kang-Deog Suh and Hashimoto, K. and
   Sung-Tae Ahn and Miyamoto, J.},
   Title = {A 120-mm<sup>2</sup> 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed},
   Journal = {Solid-State Circuits, IEEE Journal of},
   Volume = {32},
   Number = {5},
   Pages = {670-680},
   Note = {0018-9200},
   Year = {1997} }



@inproceedings{flash:HRK+2007,
   Author = {Jin-Woo Han and Seong-Wan Ryu and Chungjin Kim and Sungho Kim and Maesoon Im and Sung Jin Choi and Jin Soo Kim and Kwang Hee
   Kim and Gi Sung Lee and Jae Sub Oh and Myeong Ho Song and Yun Chang Park and Jeoung Woo Kim and Yang-Kyu Choi},
   Title = {A Unified-RAM (URAM) Cell for Multi-Functioning Capacitorless DRAM and NVM},
   BookTitle = {Electron Devices Meeting, 2007. IEDM 2007. IEEE International},
   Pages = {929-932},
   Year = {2007} }



@inproceedings{flash:KKY+2008,
   Author = {Kanda, K. and Koyanagi, M. and Yamamura, T. and Hosono, K. and Yoshihara, M. and Miwa, T. and Kato, Y. and Mak, A. and Siu Lung, Chan
   and Tsai, F. and Cernea, R. and Binh, Le and Makino, E. and Taira, T. and Otake, H. and Kajimura, N. and Fujimura, S. and Takeuchi, Y. and
   Itoh, M. and Shirakawa, M. and Nakamura, D. and Suzuki, Y. and Okukawa, Y. and Kojima, M. and Yoneya, K. and Arizono, T. and Hisada, T. and
   Miyamoto, S. and Noguchi, M. and Yaegashi, T. and Higashitani, M. and Ito, F. and Kamei, T. and Hemink, G. and Maruyama, T. and Ino, K. and
   Ohshima, S.},
   Title = {A 120mm<sup>2</sup> 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology},
   BookTitle = {Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International},
   Pages = {430-625},
   Year = {2008} }



@article{flash:SSL+1995,
   Author = {Kang-Deog, Suh and Byung-Hoon, Suh and Young-Ho, Lim and Jin-Ki, Kim and Young-Joon, Choi and Yong-Nam, Koh and Sung-Soo, Lee and
   Suk-Chon, Kwon and Byung-Soon, Choi and Jin-Sun, Yum and Jung-Hyuk, Choi and Jang-Rae, Kim and Hyung-Kyu, Lim},
   Title = {A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme},
   Journal = {Solid-State Circuits, IEEE Journal of},
   Volume = {30},
   Number = {11},
   Pages = {1149-1156},
   Note = {0018-9200},
   Year = {1995} }



@inproceedings{flash:KRM2008,
   Author = {Kgil, T. and Roberts, D. and Mudge, T.},
   Title = {Improving NAND Flash Based Disk Caches},
   BookTitle = {Computer Architecture, 2008. ISCA '08. 35th International Symposium on},
   Pages = {327-338},
   Year = {2008}
}



@article{flash:LPA+2001,
   Author = {Larcher, L. and Pavan, P. and Albani, L. and Ghilardi, T.},
   Title = {Bias and W/L dependence of capacitive coupling coefficients in floating gate memory cells},
   Journal = {Electron Devices, IEEE Transactions on},
   Volume = {48},
   Number = {9},
   Pages = {2081-2089},
   Note = {0018-9383},
   Year = {2001} }



@article{flash:LPP+2002,
   Author = {Larcher, L. and Pavan, P. and Pietri, S. and Albani, L. and Marmiroli, A.},
   Title = {A new compact DC model of floating gate memory cells without capacitive coupling coefficients},
   Journal = {Electron Devices, IEEE Transactions on},
   Volume = {49},
   Number = {2},
   Pages = {301-307},
   Note = {0018-9383},
   Year = {2002} }



@inproceedings{flash:NAR+2008,
   Author = {Nobunaga, D. and Abedifard, E. and Roohparvar, F. and Lee, J. and Yu, E. and Vahidimowlavi, A. and Abraham, M. and Talreja, S. and
   Sundaram, R. and Rozman, R. and Vu, L. and Chih Liang, Chen and Chandrasekhar, U. and Bains, R. and Viajedor, V. and Mak, W. and Choi, M. and
   Udeshi, D. and Luo, M. and Qureshi, S. and Tsai, J. and Jaffin, F. and Yujiang, Liu and Mancinelli, M.},
   Title = {A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface},
   BookTitle = {Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International},
   Pages = {426-625},
   Year = {2008} }



@inproceedings{flash:OCM+2000,
   Author = {O'Shea, M. and Concannon, A. and McCarthy, K. and Lane, B. and Mathewson, A. and Slotboom, M.},
   Title = {Development and application of a macro model for flash EEPROM design},
   BookTitle = {ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International},
   Pages = {192-196},
   Year = {2000} }



@inproceedings{flash:Prince2005,
   Author = {Prince, B.},
   Title = {Trends in scaled and nanotechnology memories},
   BookTitle = {Non-Volatile Memory Technology Symposium, 2005},
   Pages = {7 pp.},
   Year = {2005} }



@misc{flash:MN2006,
   Author = {Sang Lyul, Min and Eyee Hyun, Nam},
   Title = {Current trends in flash memory technology: invited paper},
   Publisher = {IEEE Press},
   Note = {1118382332-333},
   Year = {2006} }



@article{flash:SMI+2008,
   Author = {Shibata, N. and Maejima, H. and Isobe, K. and Iwasa, K. and Nakagawa, M. and Fujiu, M. and Shimizu, T. and Honma, M. and Hoshi, S.
   and Kawaai, T. and Kanebako, K. and Yoshikawa, S. and Tabata, H. and Inoue, A. and Takahashi, T. and Shano, T. and Komatsu, Y. and Nagaba, K.
   and Kosakai, M. and Motohashi, N. and Kanazawa, K. and Imamiya, K. and Nakai, H. and Lasser, M. and Murin, M. and Meir, A. and Eyal, A. and
   Shlick, M.},
   Title = {A 70 nm 16 Gb 16-Level-Cell NAND flash Memory},
   Journal = {Solid-State Circuits, IEEE Journal of},
   Volume = {43},
   Number = {4},
   Pages = {929-937},
   Note = {0018-9200},
   Year = {2008}
}



@misc{flash:KM2006,
   Author = {Taeho, Kgil and Trevor, Mudge},
   Title = {FlashCache: a NAND flash memory file cache for low power web servers},
   Publisher = {ACM},
   Note = {1176774103-112},
   Year = {2006}
}



@article{flash:JCC+1997,
   Author = {Tae-Sung, Jung and Do-Chan, Choi and Sung-Hee, Cho and Myong-Jae, Kim and Seung-Keun, Lee and Byung-Soon, Choi and Jin-Sun, Yum and
   San-Hong, Kim and Dong-Gi, Lee and Jong-Chang, Son and Myung-Sik, Yong and Heung-Kwun, Oh and Sung-Bu, Jun and Woung-Moo, Lee and Haq, E. and
   Kang-Deog, Suh and Ali, S. B. and Hyung-Kyu, Lim},
   Title = {A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using a NAND flash memory technology},
   Journal = {Solid-State Circuits, IEEE Journal of},
   Volume = {32},
   Number = {11},
   Pages = {1748-1757},
   Note = {0018-9200},
   Year = {1997} }



@article{flash:JCS+1996,
   Author = {Tae-Sung, Jung and Young-Joon, Choi and Kang-Deog, Suh and Byung-Hoon, Suh and Jin-Ki, Kim and Young-Ho, Lim and Yong-Nam, Koh and
   Jong-Wook, Park and Ki-Jong, Lee and Jung-Hoon, Park and Kee-Tae, Park and Jhang-Rae, Kim and Jeong-Hyong, Yi and Hyung-Kyu, Lim},
   Title = {A 117-mm<sup>2</sup> 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications},
   Journal = {Solid-State Circuits, IEEE Journal of},
   Volume = {31},
   Number = {11},
   Pages = {1575-1583},
   Note = {0018-9200},
   Year = {1996} }



@inproceedings{flash:TKA+1994,
   Author = {Tanaka, T. and Kato, M. and Adachi, T. and Ogura, K. and Kimura, K. and Kume, H.},
   Title = {High-Speed Programming and Program-Verify Methods Suitable for Low-Voltage Flash Memories},
   BookTitle = {VLSI Circuits, 1994. Digest of Technical Papers., 1994 Symposium on},
   Pages = {61-62},
      Year = {1994} }



@article{flash:TTN+1994,
   Author = {Tanaka, T. and Tanaka, Y. and Nakamura, H. and Sakui, K. and Oodaira, H. and Shirota, R. and Ohuchi, K. and Masuoka, F. and Hara,
   H.},
   Title = {A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory},
   Journal = {Solid-State Circuits, IEEE Journal of},
   Volume = {29},
   Number = {11},
   Pages = {1366-1373},
   Note = {0018-9200},
   Year = {1994} }

@article{flash:IBM2008,
   Author = {Lai, S. K.},
   Title = {Flash memories: Successes and challenges},
   Journal = {IBM Journal of Research and Development},
   Volume = {52},
   Number = {4-5},
   Pages = {529},
      Year = {2008} }

@inproceedings{flash:TKF+2006,
   Author = {Takeuchi, K. and Kameda, Y. and Fujimura, S. and Otake, H. and Hosono, K. and Shiga, H. and Watanabe, Y. and Futatsuyama, T. and Shindo, Y. and Kojima, M. and Iwai, M. and Shirakawa, M. and Ichige, M. and Hatakeyama, K. and Tanaka, S. and Kamei, T. and Jia-Yi, Fu and Cernea, A. and Yan, Li and Higashitani, M. and Hemink, G. and Sato, S. and Oowada, K. and Shih-Chung, Lee and Hayashida, N. and Jun, Wan and Lutze, J. and Shouchang, Tsao and Mofidi, M. and Sakurai, K. and Tokiwa, N. and Waki, H. and Nozawa, Y. and Kanazawa, K. and Ohshima, S.},
   Title = {A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput},
   BookTitle = {Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International},
   Pages = {507-516},
      Year = {2006} }

@inproceedings{flash:MCP+1985,
   Author = {Mukherjee, S. and Chang, T. and Pang, R. and Knecht, M. and Hu, D.},
   Title = {A single transistor EEPROM cell and its implementation in a 512K CMOS EEPROM},
   BookTitle = {Electron Devices Meeting, 1985 International},
   Volume = {31},
   Pages = {616-619},
      Year = {1985} }

@article{flash:WJ1996,
   Author = {Wilton, S. J. E. and Jouppi, N. P.},
   Title = {CACTI: an enhanced cache access and cycle time model},
   Journal = {Solid-State Circuits, IEEE Journal of},
   Volume = {31},
   Number = {5},
   Pages = {677-688},
   Note = {0018-9200},
   Year = {1996} }

@misc{flash:micron,
    Author = {{Micron~NAND~Flash~Product}},
    Title = {http://www.micron.com/products/nand/}
    }

@misc{flash:itrs,
    Author = {{International Technology Roadmap for Semiconductors}},
    Title = {{Process Integration, Devices, and Structures 2007 Edition}}
    }

@misc{flash:fep,
    Author = {{International Technology Roadmap for Semiconductors}},
    Title = {{Front End Process 2007 Edition}}
    }

@inproceedings{flash:ISN+1999,
   Author = {Imamiya, K. and Sugiura, Y. and Nakamura, H. and Himeno, T. and Takeuchi, K. and Ikehashi, T. and Kanda, K. and Hosono, K. and Shirota, R. and Aritome, S. and Shimizu, K. and Hatakeyama, K. and Sakui, K.},
   Title = {A 130 mm<sup>2</sup> 256 Mb NAND flash with shallow trench isolation technology},
   BookTitle = {Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International},
   Pages = {112-113},
   Year = {1999} }

@inproceedings{flash:MRM+2006,
   Author = {Micheloni, R. and Ravasio, R. and Marelli, A. and Alice, E. and Altieri, V. and Bovino, A. and Crippa, L. and Di Martino, E. and D'Onofrio, L. and Gambardella, A. and Grillea, E. and Guerra, G. and Kim, D. and Missiroli, C. and Motta, I. and Prisco, A. and Ragone, G. and Romano, M. and Sangalli, M. and Sauro, P. and Scotti, M. and Won, S.},
   Title = {{A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput}},
   BookTitle = {Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International},
   Pages = {497-506},
      Year = {2006} }
